1. Field of the Invention
The present invention relates to a built-up printed circuit board with stacked via-holes, and more particularly to a built-up printed circuit board having stacked micro via-holes formed therethrough, each of which is provided for interconnection between layers in the printed circuit board manufactured by a build-up process, and in each of which liquefied resin or conductive paste is filled. The present invention also relates to a method for manufacturing such a built-up printed circuit board with stacked via-holes.
2. Description of the Related Art
As well known to those skilled in the art, an inter-layer structure of a multi-layered printed circuit board has become more complicated in recent years as electronic appliances have become smaller and thinner, and yet have higher density. Also, it is required to develop a method for performing electrical conduction between layers in a high-density wiring printed circuit board to carry out a high-speed signal process in such a small-sized (light, thin, and small) electronic appliance.
In the case of a built-up printed circuit board, micro via-holes, i.e., blind via-holes are formed through the built-up printed circuit board for performing selective electrical conduction between layers in the built-up printed circuit board.
The micro via-holes generally include staggered via-holes, O-ring via-holes, and stacked via-holes.
FIGS. 1a and 1b are cross sectional views of staggered micro via-holes and O-ring micro via-holes, respectively.
In the case of the staggered micro via-holes as shown in FIG. 1a, a via-hole is first formed on a thin copper layer 1 by means of a laser drill, and a plated layer 2 is formed on the via-hole and the thin cooper layer 1. Subsequently, another via-hole is formed on the plated layer 2 in a vicinity of the first formed via-hole.
In the case of the O-ring micro via-holes as shown in FIG. 1b, a via-hole is first formed on a thin copper layer 1 by means of a laser drill, and then another via-hole having a diameter larger than that of the first formed via-hole is concentrically formed around the first formed via-hole.
FIGS. 2a to 2c are cross sectional views of various kinds of stacked micro via-holes, respectively. FIG. 2a shows stacked micro via-holes filled with copper, FIG. 2b shows stacked micro via-holes filled with resin or paste, and FIG. 2c shows stacked micro via-holes formed by copper bumps. A “via on via” technology, which provides stacked via-holes comprising a via-hole formed on another via-hole, is one of technologies applicable to all future printed circuit boards. The “via on via” technology is now under further improvement in various ways by several manufacturers of printed circuit boards.
Technologies for stacking micro via-holes formed by means of the laser drill generally include a method for filling copper into the micro via-holes, and AGP and NMBI (Neo Manhattan Bump Interconnection) methods for forming copper bumps, respectively. Especially, the NMBI method, on which North Corporation in Japan has a patent right, is a leading-edge technology for interconnecting interlayer signals in a multi-layered printed circuit board by means of copper bumps instead of the laser drill. However, the aforesaid technologies require investment in large-scale facilities, are not adaptable to produce the printed circuit boards in large quantities due to disparities between the manufacturing processes of these technologies and the existing standardized manufacturing process, and do not appropriately utilize the existing facilities, which requires vast investment in new large-scale facilities.
FIGS. 3a to 3g are cross sectional views respectively showing consecutive steps of a conventional method for manufacturing a built-up printed circuit board comprising the steps of filling via-holes using a copper plating process, and stacking the via-holes filled with the copper.
On first thin copper layers 23, each of which has a circuit pattern formed thereon, are first formed first insulating layers 24 made of film-shaped resin coated clad (RCC) or thermally curable (TC) resin, as shown in FIG. 3a. The first thin copper layers 23 are formed on the top and bottom surfaces of prepreg 21, respectively. Each of the first thin copper layers 23 has a prescribed circuit pattern formed thereon by means of an etching process.
Second, a plurality of micro via-holes 25 are formed through the first insulating layers 24 to the first thin copper layers 23 by means of a laser drill, as shown in FIG. 3b. A CO2 laser or an Nd-YAG laser may be used for forming the micro via-holes.
Third, via-hole filling copper plated layers 26 are formed on the micro via-holes 25, as shown in FIG. 3c. At the same time, the copper plated layers 26 are also formed on the first insulating layers 24, and a circuit pattern is formed on each of the copper plated layers 26 above the micro via-holes by means of an etching process.
Fourth, second insulating layers 27, which are made of film-shaped resin coated clad (RCC) or thermally curable (TC) resin, are formed on the copper plated layers 26 having circuit patterns formed thereon, respectively, as shown in FIG. 3d. 
Fifth, a plurality of micro via-holes 28 are formed through the second insulating layers 27 to the copper plated layers 26 by means of the laser drill, as shown in FIG. 3e. Subsequently, via-hole filling copper plated layers 29 are formed on the micro via-holes 28 and on the second insulating layers 27, as shown in FIG. 3f. 
Finally, a circuit pattern is formed on each of the copper plated layers 29 above the micro via-holes 28 by means of an etching process, as shown in FIG. 3g. 
As described above, a multi-layered printed circuit board is manufactured by repeatedly building up different printed circuit board units.
FIGS. 4 to 6 are cross sectional views respectively illustrating several problems raised in forming micro via-holes according to the conventional art.
As shown in FIG. 4, an air void 44 may be formed in a micro via-hole 43 when a via-hole filling copper plated layer 42 is formed on a thin copper layer 41 (Refer to FIGS. 3c and 3f).
As shown in FIG. 5, a micro via-hole 49, which is supposed to be concentrically formed above another micro via-hole 47, may deviate from the micro via-hole 47 at a interlayer eccentric distance A, by which electrical interconnection between layers in the multi-layered printed circuit board may be cut off.
As shown in FIG. 6, a dimple 54 may be formed in a micro via-hole 53 when a via-hole filling copper plated layer 52 is formed on a thin copper layer 51. The level of the copper plated layer 52 on the micro via-hole 53 is different from that of the cooper plated layer 52 in a vicinity of the micro via-hole 53 because of the dimple 54.
FIGS. 7a to 7d are photographs respectively showing the aforesaid problems mentioned with reference to FIGS. 4 to 6.
FIG. 7a shows a micro via-hole 62 formed on a copper plated layer 61 after another micro via-hole is filled with the copper, and FIG. 7b shows the micro via-hole filled with copper of FIG. 7a in detail. It can be seen from FIGS. 7a and 7b that the stacked micro via-holes deviate from each other.
FIG. 7c shows that an air void 63 is formed in a micro via-hole after the micro via-hole has been filled with copper. It can be seen from FIG. 7c that the via-hole is not completely filled with the copper because of the air void 63.
FIG. 7d shows that a dimple 64 is formed in a micro via-hole after the micro via-hole has been filled with copper. It can be seen from FIG. 7d that the level of a copper plated layer on the micro via-hole is different from that of the cooper plated layer in a vicinity of the micro via-hole because of the dimple 64.
In the aforesaid build-up process for manufacturing the printed circuit board, the micro via-hole is formed by means of the laser drill, and the micro via-hole is filled with the copper. At this time, a new plating process is added to the build-up process, which increases the cost of manufacturing the printed circuit board.